1. Field of the Invention
This invention relates to electrically programmable read only memory (EPROM) and, more particularly, to methods and apparatus for erasing small portions of EPROMs using flash techniques.
2. History of the Prior Art
Electrically programmable read only memory (EPROM) has been used for many different purposes. These memories provide a quick and relatively inexpensive way of furnishing read-only memory. These memories are available in arrays up to four megabytes. One unfortunate aspect of such memories is the difficulty of reprogramming. In general, such memories can only be erased by the manufacturer using ultra violet light, and the erasure is of all the data held in memory.
Because it is often desirable to reprogram read only memory and it is also desirable that this be done without the need to return the memory to the manufacturer, advanced forms of EPROMs have been developed. For example, electrically erasable programmable read only memories (EEPROMs) have been developed which allow the read only memory to be erased at the byte level. This facility allows erasure to be done without returning the memory to the manufacturer. It also allows most of the information already in memory to be retained, and only the specific information which needs change to be changed. See, for example, U.S. Pat. No. 4,023,158 for a discussion of such EEPROM cells and U.S. Pat. No. 4,266,283 for a discussion of the related circuitry. These memories, however, are always larger in chip size than are EPROM cells due to the larger cell necessary to implement EEPROM specific functionality. They are available only in sizes up to approximately one megabits.
Recently, a new electrically erasable programmable read only memory called flash EEPROM (FEEPROM) has been devised. Such a memory array is disclosed in U.S. patent application Ser. No. 667,905, entitled Low Voltage EEPROM Cell, Lai et al, filed Nov. 2, 1984, and assigned to the assignee of the present invention. FEEPROM may be electrically erased without returning the memory to the manufacturer. FEEPROM is available in memory arrays up to four megabytes. A difficulty with FEEPROM, however, is that it operates by applying a high voltage to the source terminals of all of the transistors (cells) used in the memory. Because these source terminals are all connected by metallic busing in the array, only the entire array may be erased. This requires that the entire board be reprogrammed once it has been erased.
It has been found possible to erase blocks of FEEPROM by physically separating those blocks during chip layout into groups (blocks) of cells which may be erased together. This reduces the reprogramming effort to some extent but it may be used only in a limited manner. The individual blocks of cells must be physically isolated on the silicon in order to allow these blocks to be flash erased separately. The separation requirement significantly increases the size of the silicon chip. Consequently, dividing the array into a finer granularity is almost economically impossible. Because large chips cannot be divided into these blocks, a very substantial amount of useful information (e.g., one-fourth) in memory must be reprogrammed in making any small change in memory.